The objective of this one-day workshop is to investigate opportunities in accelerating data management systems and workloads (which include traditional OLTP, data warehousing/OLAP, ETL, Streaming/Realtime, and XML/RDF Processing) using CPU (e.g., commodity and specialized Multi-core, Many-core, GPUs, and FPGAs), storage systems (e.g., Storage-class Memories like SSDs and Phase-change Memory), and multicore programming strategies like OpenCL.

The current data management scenario is characterized by the following trends: traditional OLTP and OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data, complex queries under real-time constraints, etc.); applications are becoming far more distributed, often consisting of different data processing components; non-traditional domains such as bio-informatics, social networking, mobile computing, sensor applications, gaming are generating growing quantities of data of different types; economical and energy constraints are leading to greater consolidation and virtualization of resources; and analyzing vast quantities of complex data is becoming more important than traditional transactional processing.

At the same time, there have been tremendous improvements in the CPU and memory technologies. Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple application domains. Commodity systems are increasingly using multi-core processors with more than 4 cores per chip and enterprise-class systems are using processors with at least 32 cores per chip. Specialized multi-core processors such as the Cell and GPUs have brought the computational capabilities of supercomputers to cheaper commodity machines. On the storage front, FLASH-based solid state devices (SSDs) are becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like Phase-change memory are on the near-term horizon and can be game-changers in the way data is stored and processed.

In spite of the trends, currently there is limited usage of these technologies in data management domain. Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to evaluate applications in a holistic manner to ensure effective utilization of CPU and memory resources. This workshop aims to understand impact of modern hardware technologies on accelerating core components of data management workloads. Specifically, the workshop hopes to explore the interplay between overall system design, core algorithms, query optimization strategies, programming approaches, performance modelling and evaluation, etc., from the perspective of data management applications.

The suggested topics of interest include, but are not restricted to:

• Hardware and System Issues in Domain-specific Accelerators
• New Programming Methodologies for Data Management Problems on Modern Hardware
• Query Processing for Hybrid Architectures
• Autonomic Tuning for Data Management Workloads on Hybrid Architectures
• Algorithms for Accelerating Multi-modal Multi-tiered Systems
• Energy Efficient Software-Hardware Co-design for Data Management Workloads
• Parallelizing non-traditional (e.g., graph mining) workloads
• Algorithms and Performance Models for modern Storage Sub-systems
• Data Layout Issues for Modern Memory and Storage Hierarchies
• New Benchmarking Methodologies for Storage-class Memories

• Paper Submission: June 25, 2010             *** NOTE NEW DATE ***
• Notification of Acceptance: July 23, 2010
• Camera-ready Submission: August 9, 2010
• Workshop Date: September 13, 2010

The workshop proceedings will be published by VLDB.

Submission Site 

All submissions will be handled electronically via EasyChair.

Formatting Guidelines 

It is the authors' responsibility to ensure that their submissions adhere strictly to the VLDB format detailed here. In particular, it is not allowed to modify the format with the objective of squeezing in more material. Submissions that do not comply with the formatting detailed here will be rejected without review. 

The paper length is limited to 8 pages. You are permitted a 4 page appendix beyond these 8 pages. However, reviewers are not required to read this appendix, and the paper should be self-contained, complete and understandable within the 8 pages. Typically, it is appropriate to place proofs, algorithm pseudocode, data set descriptions, etc. in the appendix. It is usually not appropriate to move definitions, theorems, figures, bibliography, and experimental results to the appendix. Any references to the appendix from the main paper should only be in the nature of "for additional detail see..". In particular, there should be nothing in the appendix that is necessary for a reader to understand the paper. This 8+4 page rule applies to both submissions and camera-ready.  

For LaTeX

VLDB provides a style template that is based on the ACM SIG Proceedings Style. You can download all necessary files here:

* The LaTeX document class vldb.cls

* A sample LaTeX document vldb_sample.tex

* Some pdf files that are used as figures flies.pdf, fly.pdf, rosette.pdf

* An example .bib file sigproc.bib

* A sample output document vldb_sample.pdf

For your convenience, all these files are packed together into a .zip file to download: vldb_format.zip.

For Microsoft Word

Please use this document vldb_sample.doc as template for your paper.

Workshop Co-Chairs

• Rajesh Bordawekar, IBM T.J. Watson Research Center
• Christian A. Lang, IBM T.J. Watson Research Center

       For questions regarding the workshop please send email to contact@adms-conf.org.

Program Committee

• David Bader, Georgia Tech
• Roberto Bayardo, Google
• Brian Cooper, Yahoo! Research
• John Davis, Microsoft Research
• Pradeep Dubey, Intel
• Michael Garland, NVIDIA Research
• Bugra Gedik, IBM Watson Research
• Goetz Graefe, HP Labs
• C Mohan, IBM Almaden Research
• Bongki Moon, University of Arizona
• Jens Teubner, ETH Zürich
• Philip S. Yu, University of Illinois, Chicago