The objective of this one-day workshop is to investigate opportunities in accelerating data management systems and analytics workloads (which include traditional OLTP, data warehousing/OLAP, ETL, Streaming/Real-time, Analytics (including Machine Learning), and HPC/Deep Learning) using processors (e.g., commodity and specialized Multi-core, GPUs, FPGAs, and ASICs), storage systems (e.g., Storage-class Memories like SSDs and Phase-change Memory), and programming models like MapReduce, Spark, CUDA, OpenCL, and OpenACC.

The current data management scenario is characterized by the following trends: traditional OLTP and OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data, complex queries under real-time constraints, etc.); applications are becoming far more distributed, often consisting of different data processing components; non-traditional domains such as bio-informatics, social networking, mobile computing, sensor applications, gaming are generating growing quantities of data of different types; economical and energy constraints are leading to greater consolidation and virtualization of resources; and analyzing vast quantities of complex data is becoming more important than traditional transactional processing.

At the same time, there have been tremendous improvements in the CPU and memory technologies. Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple application domains. Commodity systems are increasingly using multi-core processors with more than 6 cores per chip and enterprise-class systems are using processors with 8 cores per chip, where each core can execute upto 4 simultaneous threads. Specialized multi-core processors such as the GPUs have brought the computational capabilities of supercomputers to cheaper commodity machines. On the storage front, non-volatile solid state devices (SSDs) are becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like DNA storage are on the near-term horizon and can be game-changers in the way data is stored and processed.

In spite of the trends, currently there is limited usage of these technologies in data management domain. Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to evaluate applications in a holistic manner to ensure effective utilization of CPU and memory resources. This workshop aims to understand impact of modern hardware technologies on accelerating core components of data management workloads. Specifically, the workshop hopes to explore the interplay between overall system design, core algorithms, query optimization strategies, programming approaches, performance modelling and evaluation, etc., from the perspective of data management applications.

The suggested topics of interest include, but are not restricted to:

• Hardware and System Issues in Domain-specific Accelerators
• New Programming Methodologies for Data Management Problems on Modern Hardware
• Query Processing for Hybrid Architectures
• Large-scale I/O-intensive (Big Data) Applications
• Parallelizing/Accelerating Machine Learning/Deep Learning Workloads
• Autonomic Tuning for Data Management Workloads on Hybrid Architectures
• Algorithms for Accelerating Multi-modal Multi-tiered Systems
• Energy Efficient Software-Hardware Co-design for Data Management Workloads
• Parallelizing non-traditional (e.g., graph mining) workloads
• Algorithms and Performance Models for modern Storage Sub-systems
• Exploitation of specialized ASICs
• Novel Applications of Low-Power Processors and FPGAs
• Exploitation of Transactional Memory for Database Workloads
• Exploitation of Active Technologies (e.g., Active Memory, Active Storage, and Networking)
• New Benchmarking Methodologies for Accelerated Workloads
• Applications of HPC Techniques for Data Management Workloads
• Acceleration in the Cloud Environments
• DNA-inspired storage and processing
• Exploitation of Quantum Technologies

Organization

Workshop Co-Chairs

• Rajesh Bordawekar, IBM T.J. Watson Research Center
• Tirthankar Lahiri, Oracle

       For questions regarding the workshop please send email to contact@adms-conf.org.

Program Committee

• Bharat Sukhwani, IBM Research
• John Owens, University of California, Davis
• Nesime Tatbul, Intel Labs and MIT
• Ran Rui, University of South Florida
• Lucas Villa Real, IBM Research Brazil
• Wei Wei Gong, Oracle
• Neelam Goyal, Snowflake Computing
• Gordon Moon, Ohio State University
• Raja Appuswamy, Eurecom
• Markus Dreseler, HPI
• Diego Tome, CWI
• Rajkumar Sen, Blitz.io
• Arun Raghavan, Oracle Labs
• Carsten Binnig, TU Darmstadt
• BingShen He, NUS

Keynote Presentations

AI: What Makes it Hard and Fun!

Pradeep Dubey, Intel

Abstract: The confluence of massive data with massive compute is unprecedented. This coupled with recent algorithmic breakthroughs, we are now at the cusp of a major transformation. This transformation has the potential to disrupt a long-held balance between humans and machine where all forms of number crunching is left to computers, and most forms of decision-making is left to us humans. This transformation is spurring a virtuous cycle of compute which will impact not just how we do computing, but what computing can do for us. In this talk, I will discuss some of the application-level opportunities and system-level challenges that lie at the heart of this intersection of traditional high-performance computing with emerging data-intensive computing.

Bio: Pradeep Dubey is an Intel Senior Fellow and Director of Parallel Computing Lab (PCL), part of Intel Labs. His research focus is on defining computer architectures that can efficiently handle emerging machine learning/artificial intelligence, and traditional HPC applications for data-centric computing environments. Dubey previously worked at IBM's T.J. Watson Research Center, and Broadcom Corporation. He has made contributions to the design, architecture, and application-performance of various microprocessors, including IBM® Power PC*, Intel® i386TM, i486TM, Pentium® and Xeon®, line of processors. He holds 36 patents, has published over 100 technical papers, won the Intel Achievement Award in 2012 for Breakthrough Parallel Computing Research, and was honored with Outstanding Electrical and Computer Engineer Award from Purdue University in 2014. Dr. Dubey received a PhD in electrical engineering from Purdue University. He is a Fellow of IEEE.

Challenges and Opportunities for Acceleration in a Cloud-Native Data Warehouse

Berni Schiefer, Amazon Web Services

Abstract: In this talk we will take a fresh look at techniques that can be used to accelerate ETL/ELT and Query Processing in a data warehouse. There are both unique opportunities, but also special challenges, for a Cloud-Native Data Warehouse. We will use a Cloud-Native Data Warehouse, Amazon Redshift, as our working example to illustrate what needs acceleration, what hardware and software techniques might apply and what unique opportunities and challenges exist for a Cloud-Native Data Warehouse.

Bio: Berni Schiefer is a Senior Development Manager for EMEA at Amazon Web Services, leading the Amazon Redshift development team in Berlin, Germany. Redshift is Amazon's fully managed, petabyte-scale data warehouse service. The Berlin team focusses on Redshift Performance and Scalability, SQL Query Compilation and Redshift Spectrum. Redshift Spectrum enables running Redshift SQL queries against very large volumes of data in Amazon S3. Redshift Concurrency Scaling adds transient capacity to running Redshift clusters to elastically handle heavy demand from concurrent users and queries. Previously, Berni was an IBM Fellow working in the area of Private Cloud, Db2, Db2 Warehouse, BigSQL, with a focus on SQL-based engines, query optimization and performance.

2019: GPU Odyssey

Nikolay Sakharnykh, Nvidia

Abstract: Today’s GPUs are no longer just video accelerators from 20 years ago crunching pixels and running a static graphics pipeline. They are complex “mini” supercomputers with lots of diverse high-throughput computational cores used to accelerate critical computational blocks in ray tracing, deep learning, and HPC workloads. The GPU programming models and tools are constantly evolving enabling developers to use the new capabilities and more efficiently utilize the hardware. NVIDIA RTX Technology provides a simple, recursive, and flexible pipeline for accelerating ray tracing algorithms, inspiring developers to explore new RTX applications and take advantage of the modern GPU architecture. High throughput computations demand high memory bandwidth. GPUs are pushing the limits for memory bandwidth approaching a terabyte per second rate, which makes them ideal for accelerating data analytics workloads. Core database operations, such as joins and aggregations, map naturally to the GPU architecture and, coupled with fast compression and NVLINK interconnect, enable running the most complex queries on the GPU, not possible before.

Bio: Nikolay Sakharnykh is a Principal AI Developer Technology Engineer at NVIDIA. He started tinkering with GPUs more than 15 years ago, and has been working on optimizing applications on the GPU for more than 10 years. He has expertise in many computational domains, including real-time graphics, HPC, graph and data analytics. He’s closely working with many internal groups at NVIDIA to advance the architecture and software. His primary focus last few years has been novel memory management techniques.

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Workshop Program (Emerald Bay)

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Session 1 (9-10.30 am)

• (9-9.25 am) Experimental Study of Memory Allocation for High-Performance Query Processing, Dominik Durner, Viktor Leis, Friedrich-Schiller-Universität Jena and Thomas Neumann, TU Munich. (Slides)

• (Keynote Presentation: 9.30-10.30 am) AI: What Makes it Hard and Fun!, Pradeep Dubey, Intel

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Coffee Break (10.30 -11 am)

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Session 2 (11 am -12.30 pm)

• (11 - 11.25 am) GPU Accelerated Top-K Selection With Efficient Early Stopping, Vasileios Zois, Vassilis J. Tsotras, Wallid A. Najjar. University of California, Riverside. (Slides)

• (11.25 - 11.50 am) A Study on Database Cracking with GPUs, Eleazar Leal, University of Minnesota, and Le Gruenwald, University of Oklahoma. (Slides)

• (11.50 am - 12.15 pm) Efficient Quadtree Construction for Indexing Large-Scale Point Data on GPUs: Bottom-Up vs. Top-Down, Jianting Zhang, City University of New York, and Le Gruenwald, University of Oklahoma. (Slides)

• (12.15 - 12.40 pm) Accelerating Regular Path Queries using FPGA, Kento Miura, Department of Computer Science University of Tsukuba, Toshiyuki Amagasa and Hiroyuki Kitagawa, Center for Computational Sciences University of Tsukuba. (Slides)

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Lunch Break (12.30-2 pm)

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Session 3 (2-3.30 pm)

• (2 -2.25 pm) Computational Storage For Big Data Analytics, Balavinayagam Samynathan, Keith Chapman, Mehdi Nik, Behnam Robatmili, Shahrzad Mirkhani and Maysam Lavasani, Bigstream. (Slides)

• (Keynote Presentation: 2.30- 3.30 pm) Challenges and Opportunities for Acceleration in a Cloud-Native Data Warehouse, Berni Schiefer, Amazon Web Services

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Coffee Break (3.30-4 pm)

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Session 4 (4-5.30 pm)

• (4- 4.25 pm) High-Performance In-Network Data Processing, Jaco Hofmann, Lasse Thostrup, Tobias Ziegler, Carsten Binnig and Andreas Koch, TU Darmstadt. (Slides)

• (Keynote Presentation: 4.30- 5.30 pm) 2019: GPU Odyssey, Nikolay Sakharnykh, Nvidia (Slides)

Important Dates

• Paper Submission: Monday, 10 June, 2019, 9 pm PST
• Notification of Acceptance: Friday, 28 June, 2019
• Camera-ready Submission: Friday, 26 July, 2019
• Workshop Date: Monday, 26 August, 2019

Submission Site 

All submissions will be handled electronically via EasyChair.

Formatting Guidelines 

We will use the same document templates as the VLDB19 conference. You can find them here.

It is the authors' responsibility to ensure that their submissions adhere strictly to the VLDB format detailed here. In particular, it is not allowed to modify the format with the objective of squeezing in more material. Submissions that do not comply with the formatting detailed here will be rejected without review. 

As per the VLDB submission guidelines, the paper length for a full paper is limited to 12 pages, excluding bibliography. However, shorter papers (at least 6 pages of content) are encouraged as well.