The objective of this one-day workshop is to investigate opportunities in accelerating data management
systems and workloads (which include traditional OLTP, data
Analytics, and XML/RDF Processing) using processors (e.g., commodity and specialized Multi-core, GPUs,
FPGAs, and ASICs), storage systems (e.g., Storage-class Memories like SSDs and
Phase-change Memory), and
programming models like MapReduce, GraphLab, CUDA, OpenCL, and OpenACC.
The current data management scenario is characterized by the following trends: traditional OLTP and
OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data,
complex queries under real-time constraints, etc.); applications are becoming far more distributed, often
consisting of different data processing components; non-traditional domains such as bio-informatics, social
networking, mobile computing, sensor applications, gaming are generating growing quantities of data of
different types; economical and energy constraints are leading to greater consolidation and virtualization
of resources; and analyzing vast quantities of complex data is becoming more important than traditional
At the same time, there have been tremendous improvements in the CPU and memory technologies.
Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple
application domains. Commodity systems are increasingly using multi-core processors with more than 6
cores per chip and enterprise-class systems are using processors with 8 cores per chip,
where each core can execute
simultaneous threads. Specialized
multi-core processors such as the GPUs have brought the computational capabilities of supercomputers
to cheaper commodity machines. On the storage front, FLASH-based solid state devices (SSDs) are
becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like Phase-change
memory are on the near-term horizon and can be game-changers in the way data is stored and processed.
In spite of the trends, currently there is limited usage of these technologies in data management domain.
Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to
evaluate applications in a holistic manner to ensure effective utilization of CPU and memory resources. This
workshop aims to understand impact of modern hardware technologies on accelerating core components
of data management workloads. Specifically, the workshop hopes to explore the interplay between overall
system design, core algorithms, query optimization strategies, programming approaches, performance modelling
and evaluation, etc., from the perspective of data management applications.
The suggested topics of
interest include, but are not restricted to:
Every year, we choose a theme around which the keynote or panel
sessions are organized. This year, the workshop theme is
Interactions of Processor Architecture with Data Management.
- Hardware and System Issues in Domain-specific Accelerators
- New Programming Methodologies for Data Management Problems on Modern Hardware
- Query Processing for Hybrid Architectures
- Large-scale I/O-intensive (Big Data) Applications
- Parallelizing/Accelerating Analytical (e.g., Data Mining) Workloads
- Autonomic Tuning for Data Management Workloads on Hybrid Architectures
- Algorithms for Accelerating Multi-modal Multi-tiered Systems
- Energy Efficient Software-Hardware Co-design for Data Management Workloads
- Parallelizing non-traditional (e.g., graph mining) workloads
- Algorithms and Performance Models for modern Storage Sub-systems
- Exploitation of specialized ASICs
- Novel Applications of Low-Power Processors and FPGAs
- Exploitation of Transactional Memory for Database Workloads
- Exploitation of Active Technologies (e.g., Active Memory, Active
Storage, and Networking)
There will be two keynote presentations at the ADMS workshop. Dr. Pradeep Dubey, Intel Fellow and Director, Parallel Computing Lab, will talk about, "Big Data: Algorithms to Architecture
Matter Together". Rick Hetherington, Vice President, Oracle Hardware Development, will talk about
the SPARC architecture.
- Paper Submission: Friday, June 12,
2015, 11.59 pm PST.
- Notification of Acceptance: Wednesday, July 1, 2015
- Camera-ready Submission: Wednesday, July 15, 2015
- Workshop Date: Monday, August 31, 2015
The workshop proceedings will be published by VLDB and indexed via DBLP.
All submissions will be handled electronically via EasyChair.
We will use the same document templates as the VLDB15 conference. You can find them here.
It is the authors' responsibility to ensure that
their submissions adhere
strictly to the VLDB format detailed here. In particular, it is not allowed to modify the format with the objective of squeezing in more material. Submissions that do not comply with the formatting detailed here will be rejected without review.
The paper length for a full paper is limited to 12
For questions regarding the workshop please send email to email@example.com.
- Reza Azimi, Huawei
- Nipun Agarwal, Oracle Labs
- Robert Halstead, University of California, Riverside
- Rashed Bhatti, IBM Almaden Research
- Christoph Dubach, University of Edinburgh
- Franz Faerber, SAP
- Arno Jacobsen, University of Toronto
- Hyojun Kim, Datos IO, Inc
- Thomas Kissinger, TU Dresden
- Qiong Luo, HKUST
- Stefan Manegold, CWI
- Sina Merji, IBM Toronto
- Duane Merrill, Nvidia
- Rupesh Nasre, IIT Madras
- Mohammad Sadoghi, IBM Watson Research
- Nadathur Satish, Intel
- Sayantan Sur, Intel
- Sudhakar Yalamanchili, Georgia Tech
- Pinar Tozun, IBM Almaden Research
- Jianting Zhang, CUNY